Formal Synthesis, Simulation and Automatic Code Generation of Supervisory Control for a Manufacturing Cell

This paper presents an application of the supervisory control theory (SCT), initiated by Ramadge and Wohnam in the 80s, to coordinate a flexible manufacturing cell (FMC) controlled by a programmable logic controller (PLC). We show how the SCT associated with simulation and automatic code generation can help the control designer to shift focus from synthesis and implementation to the modeling stage. In SCT we look for a minimally restrictive supervisor that monitors the actions of a real system and disables those operations which would lead to an undesirable condition for the system. Such approach offers a formal solution and its results achieve the most flexible control for the plant. In this application we used the local modular approach, proposed by Queiroz and Cury in 2000, which consists of dividing the mentioned supervisor into further ones to resolve specific problems in the system, thus reducing the computational cost to obtain the controller. In the FMC test bed, workpieces coming from an input buffer or a rework station are transported by a robotic manipulator and a rotating table through the drilling, welding and quality test stations. After testing, workpieces can be approved, reworked or discarded if they are rejected twice. We modeled the FMC behavior and its specifications using generators. From these models we synthesized the supervisory control with the TCT tool and next we used the emulator DESEM to simulate the execution of the supervisors on the modeled plant. This procedure allowed us to perceive the necessary changes to the specifications and plant model. When the simulation was working in the expected way we generated a PLC code in structured text for the supervisors using an automatic code generator Ides2ST. In the implementation we applied a three level hierarchy, proposed by Queiroz and Cury in 2002, to make the interaction between the modular supervisors and the real system. Simulation made possible the debugging of the supervisor in the modeling stage, thus the errors detected during the implementation were restricted to the cell’s operational sequences. The automatic code generation reduced the implementation time of the supervisor code in PLC and transformed the supervisor implementing problems into modeling ones.